1. Field of the Invention
The present invention relates to a simulator, and more particularly to a simulator for a chemical mechanical polishing (CMP) process used in the manufacture of semiconductor devices.
2. Description of the Background Art
The miniaturization and high integration of large scale integrated circuits (LSIs) creates the tendency that circuit patterns formed on the LSIs have a minimum pattern dimension of 0.1 μm. A circuit pattern of an LSI can be formed in a manner that writes a design circuit on a transfer mask for implementing it on a semiconductor substrate by laser or electron beam, and then performs a batch optical transfer of the transfer mask pattern onto the semiconductor substrate by a projection transfer apparatus.
The resolution R of the transfer apparatus is given by the following expression:R=k1λ/NA
where k1 represents a process constant, λ represents a waveform, and NA represents a numerical aperture.
The circuit pattern is formed by the optical transfer method as described above, and a transfer in a defocus state produces a blurred image, resulting in poor image forming performance. Here, the extent of focus to which a predetermined image forming performance can be maintained is referred to as “depth of focus (DOE)” and is given by the following expression:DOF=k2λ/NA2
where k2 represents a process factor.
In the present condition that the fabrication dimension approaches 0.1 μm, the depth of focus that can be ensured optical theoretically is only about 0.3 μm.
On the other hand, repetitive processes such as selective etching and film formation are executed on the semiconductor substrate, and irregularities (substrate irregularities) occur on the surface of the semiconductor substrate.
The occurrence of substrate irregularities was not a serious problem in such semiconductor devices in which the integration degree is low and substrate irregularities are smaller than the depth of focus. However, as the fabrication dimension is smaller, the substrate irregularities have recently become larger than the depth of focus, making it difficult to obtain a predetermined image forming performance.
The substrate irregularities can be eliminated by for example the following methods: one in which some dummy patterns irrelevant to a real circuit pattern are properly disposed to increase the bulk of lower portions (i.e., dummy pattern method); and another in which a semiconductor substrate is planarized by polishing so as to cut the irregularities generated thereon by chemical mechanical polishing (CMP).
A general description of the planarization technique by CMP process is contained in, for example, “ULSI Lithography Technical Innovation,” pp71-86, issued Nov. 10, 1994 by Science Forum Corp.
With the miniaturization and high integration of LSIs as stated above, a CMP process becomes increasingly critical. To effectively execute the CMP process, there is need for simulation in consideration of various parameters. However, heretofore there is no effective simulator.